Consider a system in which 32kb memory space is implemented using four numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor. The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM. Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the processor are connected to 13 address pins of all the memory. The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four chip select signals.
These four chip select signals can be used to select one of the four memory IC at any one time. The address line A15 is used as enable for decoder. The simplified schematic memory organization is shown.
A minimum mode of 8086 configuration depicts a stand alone system of computer where no other processor is connected. This is similar to 8085 block diagram with the following difference. The Data transceiver block which helps the signals traveling a longer distance to get boosted up. Two control signals data transmit/ receive are connected to the direction input of transceiver (Transmitter/Receiver) and DEN. signal works as enable for this block. This is the same as Read cycle Timing Diagram except that the DT/R.
line goes high indicating it is a Data Transmission operation for the processor to memory / peripheral. Again DEN. line goes low to validate data and WR. line goes low, indicating a Write operation.
In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the type 8087 or another processor is interfaced with 8086. The Memory, Address Bus, Data Buses are shared resources between the two processors. The control signals for Maximum mode of operation are generated by the Bus Controller chip 8788. The three status outputs S0., S1., S2.
from the processor are input to 8788. The outputs of the bus controller are the Control Signals, namely DEN, DT/R., IORC., IOWTC., MWTC., MRDC., ALE etc. These control signals perform the same task as the minimum mode operation. However the DEN is an active HIGH signal which has to be converted to active LOW by means of an inverter.
ALE=Address Latch Enabled.(pin number 30 in 8085) 8085 has a special pin referred as ALE, which indicates whether multiplex bus functions as an address bus or a data bus. Whenever 8085 starts any new operation, ALE signal goes to logic 1 for about 1/2 clock cycle, at about the falling edge of CLK. If ALE=1 then multiplex bus functions as address bus. After that half clock cycle, it goes to logic 0 for nearly 3 or 4 clock cycles.
If ALE=0 then multiplex bus acts as a data bus. The ALE pin helps to enable the latching of lower order ADDR bus. The AD0-AD7 pins, as well as other control pins such as S0, S1, IO/M-, and the other address pins A8-A15, are setup to be correct at the falling edge of ALE. In memory mapped I/O, a chunk of the CPU's address space is reserved for accessing I/O devices.
In I/O mapped I/O, I/O devices are handled distinctly by the CPU and hence occupy a separate chunk of addresses predetermined by the CPU for I/O. In case of Memory mapped I/O the same address BUS is used for accessing both Memory (RAM) and the Registers of I/O devices. For I/O Mapped I/O, separate address BUS is used. As Address space is generally larger for Memory than I/O registers, the length of I/O address is larger in case of Memory Mapped I/O.
For a system which uses I/O Mapped I/O, there is a requirement for a extra h/w Circuitry. The current state of the processor is stored in a register called Processor Status Word(PSW).The PSW contains bits which indicate such things as whether the previous arithmetic operations produced a positive,negative or zero result. NIf a subtract instruction is followed by a 'branch on zero' instruction,then the branch will be taken if the PSW indicates that the subtraction resulted in a zero.
NMost loops,such as DO-WHILE,FOR,etc involve incrementing or decrementing a counter and repeating the loop until the counter reaches the limit.Each time the counter is changed,the result is compared with the limit,the PSW is set naccordingly,and branch is taken or not depending on the contents of the PSW. NThe 8086 microprocessor has a 16-bit PSW.Each bit of this PSW is known as a flag and 7 out of these are not used.The 9 flags are classified into control flags and condition flags. Each data transfer is 3 clock cycles.
The first cycle emits address and status, and ALE is used to strobe the low order address. Status is S0, S1, and IO/M. The second cycle sets up the transfer, either floating the data bus for a read, or drving the data bus for a write, and then initiating transfer with RD- or WR. If READY is not true at the sample point (about the middle of the second cycle) an extra cycle is appended after the second cycle, with all lines frozen, until READY goes true. The third cycle wraps up the transfer. The processor samples data one half cycle before the end of RD- for a read, and it holds the data bus valid for one half cycle after WR- for a write. Up to this point, all cycles are similar.
What matters is IO/M. If high, this is an IO read or IO write; if low, this is a memory read or memory write. However, you have to consider S0 and S1.
These are advanced status pins, along with IO/M-, that indicate what the processor is doing. They are emitted at ALE. In addition to indicating IO Read, IO Write, Memory Read, and Memory Write, you can decode Opcode Fetch, Interrupt Acknowledge, and Halt. The processor has 5 interrupts.
They are presented below in the order of their priority (from lowest to highest): INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions:. One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N. 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction). CALL instruction (3 byte instruction).
The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction. RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 002Ch (hexadecimal) address. RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 0034h (hexadecimal) address. RST7.5 is a maskable interrupt.
When this interrupt is received the processor saves the contents of the PC register into stack and branches to 003Ch (hexadecimal) address. Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 0024h (hexadecimal) address.
All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.
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